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| author | midipix <writeonce@midipix.org> | 2018-08-17 21:03:34 -0400 |
|---|---|---|
| committer | midipix <writeonce@midipix.org> | 2018-08-17 21:03:34 -0400 |
| commit | 2770a22b4621571bdc3bb6c7cb321414e2d82592 (patch) | |
| tree | 7acb1c539292b3eefeaa5ed64f05abc431ca085a /project/common.mk | |
| parent | a67c3262593be55ef0be74ce54e22449029d7e78 (diff) | |
| download | bfirm-2770a22b4621571bdc3bb6c7cb321414e2d82592.tar.bz2 bfirm-2770a22b4621571bdc3bb6c7cb321414e2d82592.tar.xz | |
added riscv target-specific (code generation) definitions.
Diffstat (limited to 'project/common.mk')
| -rw-r--r-- | project/common.mk | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/project/common.mk b/project/common.mk index fda2ae7..ffbf88d 100644 --- a/project/common.mk +++ b/project/common.mk @@ -20,6 +20,7 @@ GEN_EMITTER_SRCS = \ build/gen/ir/be/ia32/gen_ia32_emitter.c \ build/gen/ir/be/mips/gen_mips_emitter.c \ build/gen/ir/be/sparc/gen_sparc_emitter.c \ + build/gen/ir/be/riscv/gen_riscv_emitter.c \ build/gen/ir/be/TEMPLATE/gen_TEMPLATE_emitter.c \ GEN_OPCODES_SRCS = \ @@ -28,6 +29,7 @@ GEN_OPCODES_SRCS = \ build/gen/ir/be/ia32/gen_ia32_new_nodes.c \ build/gen/ir/be/mips/gen_mips_new_nodes.c \ build/gen/ir/be/sparc/gen_sparc_new_nodes.c \ + build/gen/ir/be/riscv/gen_riscv_new_nodes.c \ build/gen/ir/be/TEMPLATE/gen_TEMPLATE_new_nodes.c \ GEN_REGALLOC_SRCS = \ @@ -36,6 +38,7 @@ GEN_REGALLOC_SRCS = \ build/gen/ir/be/ia32/gen_ia32_regalloc_if.c \ build/gen/ir/be/mips/gen_mips_regalloc_if.c \ build/gen/ir/be/sparc/gen_sparc_regalloc_if.c \ + build/gen/ir/be/riscv/gen_riscv_regalloc_if.c \ build/gen/ir/be/TEMPLATE/gen_TEMPLATE_regalloc_if.c \ |